The new hierarchical design error isolation and incremental fix capabilities in the Synplify Premier software, in conjunction with enhanced continue-on-error capability, can significantly shorten design cycles by speeding up design fixes and reducing the number of iterations needed to successfully bring-up the FPGA design on the board. Synplify customers with all-vendor configurations of Synplify Pro and Premier can now target Achronix's Speedster22i HD FPGAs built on Intel's 22nm process technology with 3-D Tri-Gate transistors. For designers targeting Altera FPGAs, the new version of the Synplify Premier tool provides high reliability capabilities, such as triple modular redundancy (TMR) and automatic inference of error-correcting code (ECC) memories. For engineers targeting Xilinx 7 Series devices, new automated constraints setup assistance and checking for Xilinx's Vivado Design Suite simplifies migration from the Xilinx ISE design software, saving time and enhancing quality of results. The 2012.09 Synplify Premier release also delivers significant enhancements for engineers targeting Altera and Xilinx FPGAs and, for the first time, includes support for Achronix Speedster 22i HD FPGAs. These features enable FPGA designers and engineers deploying FPGA-based prototypes such as Synopsys' HAPS systems to cut weeks off their design project schedules.
The 2012.09 Synplify releases include new multiple error isolation and incremental fix capabilities that accelerate FPGA implementation. (Nasdaq:SNPS), a global leader accelerating innovation in the design, verification and manufacture of chips and systems, today announced the latest release of the Synopsys Synplify Pro® and Synplify® Premier FPGA synthesis tools.
Triple modular redundancy and inference of error-correcting code fault-tolerant RAMs has been added for Altera devices.New constraints setup assistance for Xilinx Vivado Design Suite users eases migration to Vivado flow, improves design performance and helps avoid constraints omissions.
New debug flows for multiple error isolation and incremental fix capabilities enable faster implementation of large FPGA designs and FPGA-based prototypes, such as Synopsys' HAPS® systems.
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